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1 ? fn9055.10 isl6526, isl6526a single synchronous buck pulse-width modulation (pwm) controller the isl6526, isl6526a make simple work out of implementing a complete control and protection scheme for a dc/dc stepdown converter. designed to drive n-channel mosfets in a synchronous buck topology, the isl6526, isl6526a integrate the cont rol, output adjustment, monitoring and protection functions into a single package. the isl6526, isl6526a provide simple, single feedback loop, voltage-mode control with fast transient response. the output voltage can be precisely regulated to as low as 0.8v, with a maximum tolerance of 1.5% over-temperature and line voltage variations. a fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. the error amplifier features a 15mhz gain-bandwidth product and 6v/s slew rate which enables high converter bandwidth for fast transient performance. the resulting pwm duty cycles range from 0% to 100%. protection from overcurrent conditions is provided by monitoring the r ds(on) of the upper mosfet to inhibit pwm operation appropriately. this approach simplifies the implementation and improves ef ficiency by eliminating the need for a current sense resistor. features ? operates from 3.3v to 5v input ? 0.8v to v in output range - 0.8v internal reference - 1.5% over load, line voltage and temperature ? drives n-channel mosfets ? simple single-loop control design - voltage-mode pwm control ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty cycle ? lossless, programmable overcurrent protection - uses upper mosfet?s r ds(on) ? converter can source and sink current ? small converter size - internal fixed frequency oscillator - isl6526: 300khz - isl6526a: 600khz ? internal soft-start ? 14 ld soic or 16 ld 5x5 qfn ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free (rohs compliant) applications ? power supplies for microprocessors -pcs - embedded controllers ? subsystem power supplies - pci/agp/gtl+ buses - acpi power control - ddr sdram bus termination supply ? cable modems, set-top boxes, and dsl modems ? dsp and core communications processor supplies ? memory supplies ? personal computer peripherals ? industrial power supplies ? 3.3v-input dc/dc regulators ? low-voltage distributed power supplies data sheet november 24, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2001-2005, 2007, 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn9055.10 november 24, 2008 ordering information part number (note) part marking temp range (c) package pkg dwg. # isl6526cbz 6526cbz 0 to +70 14 ld soic (pb-free) m14.15 isl6526cbz-t* 6526cbz 0 to +70 14 ld soic (pb-free) m14.15 isl6526acbz 6526acbz 0 to +70 14 ld soic (pb-free) m14.15 isl6526acbz-t* 6526acbz 0 to +70 14 ld soic (pb-free) m14.15 isl6526crz isl6526 crz 0 to +70 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526crz-t* isl6526 crz 0 to +70 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526acrz isl6526 acrz 0 to +70 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526acrz-t* isl6526 acrz 0 to +70 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526ibz 6526ibz -40 to +85 14 ld soic (pb-free) m14.15 isl6526ibz-t* 6526ibz -40 to +85 14 ld soic (pb-free) m14.15 isl6526aibz 6526aibz -40 to +85 14 ld soic (pb-free) m14.15 isl6526aibz -t* 6526aibz -40 to +85 14 ld soic (pb-free) m14.15 isl6526irz isl 6526irz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526irz-t* isl 6526irz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526irz-tk* isl 6526irz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526airz isl65 26airz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b ISL6526AIRZ-T* isl65 26airz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b ISL6526AIRZ-Tk* isl65 26airz -40 to +85 16 ld 5x5 qfn (pb-free) l16.5x5b isl6526eval1 isl6526 soic evaluation board isl6526eval2 isl6526 qfn evaluation board isl6526aeval1 isl6526a soic evaluation board isl6526aeval2 isl6526a qfn evaluation board *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. pinouts isl6526, isl6526a (14 ld soic) top view isl6526, isl6526a (16 ld qfn) top view 12 14 13 4 3 2 1 lgate cpvout ugate phase vcc boot gnd ct1 11 7 6 5 9 8 10 ct2 ocset fb cpgnd enable comp 1 3 4 15 cpvout ct1 ct2 ocset lgate gnd ugate boot 16 14 13 2 12 10 9 11 6 578 phase vcc cpgnd nc nc fb comp enable isl6526, isl6526a
3 fn9055.10 november 24, 2008 typical application - 3.3v input typical application - 5v input v out fb comp ugate phase boot gnd lgate isl6526, isl6526a r fb r offset c i c f r f l out d boot c boot c in c pump c hf c out ocset cpvout c bulk r ocset q 1 q 2 ct1 ct2 cpgnd enable disable vcc 3.3v v in c dcpl v out fb comp ugate phase boot gnd lgate isl6526, isl6526a r fb r offset c i c f r f l out d boot c boot c hf c out ocset cpvout c bulk r ocset q 1 q 2 ct1 ct2 cpgnd enable disable vcc +5v v in c in n/c isl6526, isl6526a
4 fn9055.10 november 24, 2008 block diagram + - + - + - oscillator inhibit pwm comparator error amp cpvout pwm gnd fb comp 0.8v oc comparator gate control logic boot ugate phase 20a fixed 300khz or 600khz lgate soft-start ocset reset (por) power-on enable + - vcc ct1 ct2 cpgnd pump charge isl6526, isl6526a
5 fn9055.10 november 24, 2008 absolute maximum rati ngs thermal information supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . +15.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.3v to vcc +0.3v operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v 10% ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 67 n/a qfn package (notes 2, 3). . . . . . . . . . 35 5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted v cc = 3.3v 5% and t a = +25c. parameter symbol test conditions min typ max units vcc supply current nominal supply i bias 6.1 6.9 7.7 ma power-on reset rising cpvout por threshol d por commercial 4.25 4.30 4.42 v industrial 4.10 4.30 4.50 v cpvout por threshold hysteresis 0.3 0.6 0.9 v oscillator frequency f osc ic = isl6526c, commercial 275 300 325 khz ic = isl6526i, industrial 250 300 340 khz ic = isl6526ac, commercial 554 600 645 khz ic = isl6526ai, industrial 524 600 650 khz ramp amplitude v osc -1.5-v p-p reference reference voltage tolerance --1.5% nominal reference voltage v ref -0.800- v charge pump nominal charge pump output v cpvout v vcc = 3.3v, no load - 5.1 - v charge pump output regulation -2- % error amplifier dc gain (note 4) - 88 - db gain-bandwidth product gbwp - 15 - mhz slew rate sr - 6 - v/s soft-start soft-start slew rate commercial 6.2 - 7.3 ms industrial 6.2 - 7.6 ms isl6526, isl6526a
6 fn9055.10 november 24, 2008 functional pin description 14 ld soic top view 16 ld 5x5 qfn top view vcc this pin provides the bias supply for the isl6526, isl6526a. connect a well-decoupled 3.3v supply to this pin. comp and fb comp and fb are the available external pins of the error amplifier. the fb pin is the in verting input of the internal error amplifier and the comp pin is the error amplifier output. these pins are used to compensate the voltage control feedback loop of the converter. gnd this pin represents the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. phase connect this pin to the upper mosfet?s source. this pin is used to monitor the voltage drop across the upper mosfet for overcurrent protection. ugate connect this pin to the upper mosfet?s gate. this pin provides the pwm-controlled gate drive for the upper mosfet. this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper mosfet has turned off. boot this pin provides ground referenced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive a logic-level n-channel mosfet. lgate connect this pin to the lower mosfet?s gate. this pin provides the pwm-controlled gate drive for the lower mosfet. this pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turned off. ocset connect a resistor (r ocset ) from this pin to the drain of the upper mosfet (v in ). r ocset , an internal 20a current source (i ocset ), and the upper mosfet on-resistance (r ds(on) ) set the converter overcurrent (oc) trip point according equation 1: an overcurrent trip cycles the soft-start function. gate drivers upper gate source current i ugate-src v boot - v phase = 5v, v ugate = 4v - -1 - a upper gate sink current i ugate-snk -1- a lower gate source current i lgate-src v vcc = 3.3v, v lgate = 4v - -1 - a lower gate sink current i lgate-snk -2- a protection/disable ocset current source i ocset commercial 182022 a industrial 16 20 22 a disable threshold v disable --0.8v note: 4. limits should be considered typi cal and are not production tested. electrical specifications recommended operating conditions, unless otherwise noted v cc = 3.3v 5% and t a = +25c. (continued) parameter symbol test conditions min typ max units 12 14 13 4 3 2 1 lgate cpvout ugate phase vcc boot gnd ct1 11 7 6 5 9 8 10 ct2 ocset fb cpgnd enable comp 1 3 4 15 cpvout ct1 ct2 ocset lgate gnd ugate boot 16 14 13 2 12 10 9 11 6 578 phase vcc cpgnd nc nc fb comp enable i peak i ocset xr ocset r ds on () ------------------------------------------------- = (eq. 1) isl6526, isl6526a
7 fn9055.10 november 24, 2008 enable this pin is the open-collector enable pin. pulling this pin to a level below 0.8v will disable the controller. disabling the isl6526, isl6526a causes the o scillator to stop, the lgate and ugate outputs to be held low, and the soft-start circuitry to re-arm. ct1 and ct2 these pins are the connections for the external charge pump capacitor. a minimum of a 0.1f ceramic capacitor is recommended for proper operation of the ic. cpvout this pin represents the output of the charge pump. the voltage at this pin is the bias voltage for the ic. connect a decoupling capacitor from this pin to ground. the value of the decoupling capacitor should be at least 10x the value of the charge pump capacitor. this pin may be tied to the bootstrap circuit as the source for creating the boot voltage. cpgnd this pin represents the signal and power ground for the charge pump. tie this pin to the ground island/plane through the lowest impedance connection available. functional description initialization the isl6526, isl6526a automatically initialize upon receipt of power. special sequencing of the input supplies is not necessary. the power-on reset (por) function continually monitors the output voltage of the charge pump. during por, the charge pump operates on a free running oscillator. once the por level is reached, the charge pump oscillator is synched to the pwm oscillator. the por function also initiates the soft-start operation after the charge pump output voltage exceeds its por threshold. soft-start the por function initiates the digital soft-start sequence. the pwm error amplifier reference is clamped to a level proportional to the soft-start voltage. as the soft-start voltage slews up, the pwm comparator generates phase pulses of increasing width that charge th e output capacitor(s). this method provides a rapid and c ontrolled output voltage rise. the soft-start sequence ty pically takes about 6.5ms. figure 1 shows the soft-start sequence for a typical application. at t0, the +3.3v vcc voltage starts to ramp-up. at time t1, the charge pump begins operation and the +5v cpvout ic bias voltage starts to ramp-up. once the voltage on cpvout crosses the por threshold at time t2, the output begins the soft-start sequence. the triangle waveform from the pwm oscillator is compared to the rising error amplifier output voltage. as the error amplifier voltage increases, the pulse width on the ugate pin increases to reach the steady-state duty cycle at time t3. shoot-through protection a shoot-through condition occurs when both the upper mosfet and lower mosfet are turned on simultaneously, effectively shorting the input voltage to ground. to protect the regulator from a shoot-t hrough condition, the isl6526, isl6526a incorporate specialized circuitry which insures that the complementary mosfets are not on simultaneously. the adaptive shoot-through pr otection utilized by the isl6526, isl6526a look at the lower gate drive pin, lgate, and the upper gate drive pin, ugate, to determine whether a mosfet is on or off. if the voltage from ugate or from lgate to gnd is less than 0.8v, then the respective mosfet is defined as being off and the complementary mosfet is turned on. this method of shoot-through protection allows the regulator to sink or source current. since the voltage of the lowe r mosfet gate and the upper mosfet gate are being measured to determine the state of the mosfet, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their res pective mosfet gates before actually implementing such measures. doing so may interfere with the shoo t-through protection. output voltage selection the output voltage can be programmed to any level between v in and the internal reference, 0.8v. an external resistor divider is used to scale the out put voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier; see figure 2. however, since the value of r1 affects the values of t he rest of the compensation components, it is advisable to keep its value less than 5k . r4 can be calculated based equation 2: if the output voltage desired is 0.8v, simply route the output back to the fb pin through r1, but do not populate r4. figure 1. soft-start interval 0v time t2 t3 t0 cpvout (5v) vcc (3.3v) v out (2.50v) (1v/div) t1 r4 r1 0.8v v out1 0.8v ? ------------------------------------- - = (eq. 2) isl6526, isl6526a
8 fn9055.10 november 24, 2008 overcurrent protection the overcurrent function protects the converter from a shorted output by using the upper mosfet on-resistance, r ds(on) , to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating a current sensing resistor. the overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r ocset ) programs the overcurrent trip le vel (see ?typical application - 3.3v input? on page 3 and ?typical application - 5v input? on page 3). an internal 20a (typical) current sink develops a voltage across r ocset that is referenced to v in . when the voltage across the upper mosfet (also referenced to v in ) exceeds the voltage across r ocset , the overcurrent function initiates a soft-start sequence. figure 3 illustrates the protection feature responding to an overcurrent event. at time t0 , an overcurrent condition is sensed across the upper mosfet . as a result, the regulator is quickly shutdown and the inte rnal soft-start function begins producing soft-start ramps. th e delay interval seen by the output is equivalent to three soft-start cycles. the fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time t1. the output is brought back into regulation by time t2, as long as the overcurrent event has cleared. had the cause of the overcurr ent still been present after the delay interval, the overcurrent condition would be sensed and the regulator would be shut down again for another delay interval of three soft-start cycles. the resulting hiccup mode style of protection would continue to repeat indefinitely. the overcurrent function will trip at a peak inductor current (i peak) determined by equation 3: where i ocset is the internal ocset current source (20a typical). the oc trip point varies mainly due to the mosfet r ds(on) variations. to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from equation 3 with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for , where i is the output inductor ripple current. for the ripple current, see equation 11 in ?output inductor selection? on page 11. a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input voltage. current sinking the isl6526, isl6526a incorpor ate a mosfet shoot-through protection method which allows a converter to sink current as well as source current. care should be exercised when designing a converter with the is l6526, isl6526a when it is known that the converter may sink current. when the converter is sinking cu rrent, it is behaving as a boost converter that is regula ting its input voltage. this means that the converter is b oosting current into the input rail of the regulator. if there is nowhere for this current to go, figure 2. output voltage selection + r1 c out +3.3v v out r4 l out isl6526, c4 q1 fb ugate vcc boot comp d1 r2 c2 c1 r3 c3 phase lgate q2 cpvout vin isl6526a figure 3. overcurrent protection response 0v time v out (2.5v) t1 t0 t2 internal soft-start function delay interval i peak i ocset x r ocset r ds on () ---------------------------------------------------- - = (eq. 3) i peak i out max () i () 2 ---------- + > isl6526, isl6526a
9 fn9055.10 november 24, 2008 (such as to other distributed loads on the rail or through a voltage limiting protection device), the capacitance on this rail will absorb the current. this situation will allow the voltage level of the input rail to increase. if the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of any components attached to the input rail, then those components may experience an irreversible failure or experience stress th at may shorten their lifespan. ensuring that there is a path for the current to flow other than the capacitance on the rail will prevent this failure mode. application guidelines layout considerations layout is very important in high frequency switching converter design. with power devices switching efficiently at 300khz or 600khz, the resulti ng current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimize the voltage spikes in the converters. as an example, consider the turn-off transition of the pwm mosfet. prior to turn-off, the mo sfet is carrying the full load current. during turn-of f, current stops flo wing in the mosfet and is picked up by the lower mosfet. any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the cr itical components, and short, wide traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using the isl6526, isl6526a. the switching components are the most critical because they switch large amounts of energy, and theref ore tend to generate large amounts of noise. next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 4 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer (usually a middle layer of the pc board) for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the gate pins to the mosfet gates should be kept short and wide enough to easily handle the 1a of drive current. the switching components should be placed close to the isl6526, isl6526a first. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper mosfet and lower mosfet and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. position the bypass capacitor, c bp , close to the vcc pin with a via directly to the ground plane. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors for both regulators should also be located as close as possible to the relevant fb pin with vias tied straight to the ground plane as required. feedback compensation figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (err or amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse width modulated (pwm) wave with an amplitude of v in at v out island on power plane layer island on circuit plane layer l out c out c in +3.3v v in key comp isl6526, isl6526a ugate r4 r 2 c bp fb gnd cpvout figure 4. printed circuit board power planes and islands r 1 boot c 2 via connection to ground plane load q1 c boot phase d1 r 3 c 3 c 1 q2 lgate phase vcc c vcc isl6526, isl6526a
10 fn9055.10 november 24, 2008 the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the isl6526, isl6526a) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. equations 6, 7, 8 and 9 relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 5. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place first zero below filter?s double pole (~75% f lc ). 3. place second zero at filter?s double pole. 4. place first pole at the esr zero. 5. place second pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin - repeat if necessary. compensation break frequency equations figure 6 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 6. using the pr eviously mentioned guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 6 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. figure 5. voltage-mode buck converter compensation design v out reference l o c o esr v in v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 1 c 2 comp v out fb z fb isl6526, isl6526a z in comparator driver detailed compensation components phase v e/a + - + - z in osc f lc 1 2 x l o x c o ----------------------------------------- - = (eq. 4) f esr 1 2 x esr x c o ------------------------------------------- = (eq. 5) f z1 1 2 r 2 c 2 ---------------------------------- = (eq. 6) f z2 1 2 x r 1 r 3 + () x c 3 ------------------------------------------------------ - = (eq. 7) f p1 1 2 x r 2 x c 1 x c 2 c 1 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = (eq. 8) f p2 1 2 x r 3 x c 3 ------------------------------------ = (eq. 9) figure 6. asymptotic bode plot of converter gain 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain modulator gain loop gain 20 v in v osc ----------------- - ?? ?? ?? log 20 r2 r1 ------- - ?? ?? log isl6526, isl6526a
11 fn9055.10 november 24, 2008 component selection guidelines charge pump capacitor selection a capacitor across pins ct1 and ct2 is required to create the proper bias voltage for the isl6526, isl6526a when operating the ic from 3.3v. selecting the proper capacitance value is important so that th e bias current draw and the current required by the mosfet gates do not overburden the capacitor. a conservative approach is presented in equation 10. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. th e filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern digital ics can produce high transient load slew rates. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor valu es are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr ava ilable in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to hi gh slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by equations 11 and 12: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the isl6526, isl6526a will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval, the difference between the inductor current and the transient current level mu st be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the re moval of load. equations 13 and 14 give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum c pump i biasandgate v cc f s ------------------------------------ 1.5 = (eq. 10) i= v in - v out f s x l v out v in x (eq. 11) v out = i x esr (eq. 12) t rise = l x i tran v in - v out (eq. 13) t fall = l x i tran v out (eq. 14) isl6526, isl6526a
12 fn9055.10 november 24, 2008 input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. the maximum rms current required by the regulator may be closely approximated using equation 15: for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge cu rrent rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge curre nt tested. mosfet selection/considerations the isl6526, isl6526a require two n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching lo ss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. thes e losses are distributed between the two mosfets according to duty factor. the switching losses seen when sour cing current will be different from the switching losses seen when sinking current. when sourcing current, the upper mosf et realizes most of the switching losses. the lower switch realizes most of the switching losses when the conv erter is sinking current (see equations 16 and 17). thes e equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower mosfet?s body diode. the gate-charge losses are dissipated by the isl6526, isl6526a and don't heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperatur e rise according to package thermal-resistance specificati ons. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. given the reduced available gate bias voltage (5v), logic-level or sub-logic-level transistors should be used for both n-mosfets. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot-through protection present aboard the isl6526, isl6526a may be circumvented by these mosfets if they have large parasitic impedances and/or capacitances t hat would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. bootstrap component selection external bootstrap components, a diode and capacitor, are required to provide sufficient gate enhancement to the upper mosfet. the internal mosfet gate driver is supplied by the external bootstrap circuitry, as shown in figure 7. the boot capacitor, c boot , develops a floating supply voltage referenced to the phase pin. this supply is refreshed each cycle, when d boot conducts, to a voltage of cpvout less the boot diode drop, v d , plus the voltage rise across q lower . just after the pwm switchi ng cycle begins and the charge transfer from the bootstrap capa citor to the gate capacitance is complete, the voltage on the bootstrap capacitor is at its lowest point during the switch ing cycle. the charge lost on the bootstrap capacitor will be equal to the charge transferred to the equivalent gate-source capacitance of the upper mosfet as shown in equation 18: i rms max v out v in ------------- - i out max 2 1 12 ------ v in v out ? lf s ----------------------------- v out v in ------------- - ?? ?? 2 + ?? ?? = (eq. 15) p lower = io 2 x r ds(on) x (1 - d) losses while sourcing current p upper io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = (eq. 16) where: d is the duty cycle = v out /v in , t sw is the combined switch on and off time, and f s is the switching frequency. losses while sinking current p lower io 2 r ds on () 1d ? () 1 2 -- - io ? v in t sw f s + = p upper = io 2 x r ds(on) x d (eq. 17) isl6526, gnd lgate ugate phase boot v in note: note: v g-s = v cc c boot d boot q upper q lower + - figure 7. upper gate drive bootstrap v g-s = v cc -v d + v d - cpvout isl6526a q gate c boot v boot1 v boot2 ? () = (eq. 18) isl6526, isl6526a
13 fn9055.10 november 24, 2008 where q gate is the maximum total gate charge of the upper mosfet, c boot is the bootstrap capacitance, v boot1 is the bootstrap voltage immediately before turn-on, and v boot2 is the bootstrap voltage immediately after turn-on. the bootstrap capacitor begins its refresh cycle when the gate drive begins to turn-off the upper mosfet. a refresh cycle ends when the upper mosfet is turned on again, which varies depending on the switching frequency and duty cycle. the minimum bootstrap capacitance can be calculated by rearranging the previous equation and solving for c boot . typical gate charge values for mosfets considered in these types of applications range from 20 to 100nc. since the voltage drop across q lower is negligible, v boot1 is simply v cpvout - v d . a schottky diode is recommended to minimize the voltage drop across the bootstrap capacitor during the on-time of the upper mosfet. initial calculations with v boot2 no less than 4v will quickly help narrow the bootstrap capacitor range. for example, consider an upper mosfet is chosen with a maximum gate charge, q g , of 100nc. limiting the voltage drop across the bootstrap capacitor to 1v results in a value of no less than 0.1f. the tolerance of the ceramic capacitor should also be considered when selecting the final bootstrap capacitance value. a fast recovery diode is recommended when selecting a bootstrap diode to reduce the im pact of reverse recovery charge loss. otherwise, the recovery charge, q rr , would have to be added to the gate charge of the mosfet and taken into consideration when calculating the minimum bootstrap capacitance. isl6526, isl6526a dc/dc converter application circuit figure 8 shows an application circuit of a dc/dc converter. detailed information on the circuit, including a complete bill of materials and circuit board description, can be found in application note an1021: http://www.intersil. com/data/an/an1021.pdf. c boot q gate v boot1 v ? boot2 ---------------------------------------------------- - = (eq. 19) component selection notes: c 3, c 8, c 9 - each 150f, panasonic eef-ue0j151r or equivalent. d1 - 30ma schottky diode, ma732 or equivalent l 1 - 1h inductor, panasonic p/n etq-p6f1rosfa or equivalent. q 1 - fairchild mosfet; itf86110dk8. 2.5v @ 5a fb comp ugate phase boot gnd lgate isl6526, isl6526a r 3 r 5 c 10 c 11 r 2 l 1 d 1 c 7 c 1 c 4 c 6 c 8, 9 ocset cpvout c 3 r 1 q 1 ct1 ct2 cpgnd vcc 3.3v c 5 c 2 c 12 r 4 gnd u 1 gnd 14 1 2 3 4 5 8 6 7 9 10 11 12 13 tp 1 tp 3 enable 9.76k 6.49k 2.26k 124 0.1f 1000pf 10f 0.22f 1f 0.1f 33pf 5600pf 8200pf 1.07k ceramic enable figure 8. 3.3v to 2.5v 5a dc/dc converter cap isl6526, isl6526a
14 fn9055.10 november 24, 2008 package outline drawing l16.5x5b 16 lead quad flat no-lead plastic package rev 2, 02/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 i dentifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 0.15 (4x) index area pin 1 6 5.00 5.00 b a pin #1 index area 16 13 4x 0.80 12x 2.4 6 4 3 . 10 0 . 15 1 cb a 0.10 m 0.33 +0.07 / -0.05 4 5 16x 0 . 60 8 9 12 1.00 max base plane seating plane 0.08 see detail "x" 0.10 c c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 ( 4 . 6 typ ) ( 3 . 10 ) ( 16x 0 .33 ) ( 16 x 0 . 8 ) ( 12x 0 . 80 ) +0.15 -0.10 isl6526, isl6526a
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9055.10 november 24, 2008 isl6526, isl6526a small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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